HW-V5-ML555-G【PDF 57/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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Clock Generation

Global Clock Inputs

Global clock inputs to the FPGA are summarized in Table 3-19 . Global clocks are

connected to FPGA bank 3.

Table 3-19:

FPGA Global Clock Inputs

FPGA Pins

L18

K17

H18

H17

H19

H20

J20 (4)

J21 (4)

G16

G15

Signal Name

LVPECL_200M_N

LVPECL_200M_P

SMA_GCLKN (2,5)

SMA_GCLKP (2,5)

LVDSCLKMOD1_P

LVDSCLKMOD1_N

SATA_MGT_GCLKP

SATA_MGT_GCLKN

SFP_MGT_GCLKN

SFP_MGT_GCLKP

Clock Source

200 MHz LVPECL oscillator Y3

200 MHz LVPECL oscillator Y3

SMA Connector J11

SMA Connector J10 (3)

Clock Synthesizer 1

Clock Synthesizer 1

Selectable: 125 MHz Oscillator or Clock Synthesizer 2

Selectable: 125 MHz Oscillator or Clock Synthesizer 2

125 MHz LVDS Oscillator

125 MHz LVDS Oscillator

L19

FPGA_GCLK_30MHZ (3) 30 MHz Oscillator

H14

J19

J14

J16 (2)

J17 (2)

H15 (4)

P0_RCLK1 (3)

P1_RCLK1 (3)

PCIBUSCLK2 (3)

PCIE_GCLK_P

PCIE_GCLK_N

SATA_MGT_CLKSEL

Port 0 Ethernet PHY Receive Clock (if the EPHY daughtercard is installed)

Port 1 Ethernet PHY Receive Clock (if the EPHY daughtercard is installed)

P1-B16 active only when the ML555 board is installed in a PCI bus

connector. Not active when the ML555 board is installed in a PCI Express

connector.

Global clock input available only if an ICS874003-02 PCI Express clock jitter

attenuator circuit is installed on the ML555 board at location U16 (not the

default board configuration). This clock is 100, 125, or 250 MHz as selected

by the CPLD controls. The default is a 250 MHz spread spectrum clock

generated from the add-in card PCI Express input clock on connector P13.

Global clock input available only if an ICS874003-02 PCI Express clock jitter

attenuator circuit is installed on the ML555 board at location U16 (this is not

the default board configuration). This clock is 100, 125, or 250 MHz as

selected by the CPLD controls. The default is a 250 MHz spread spectrum

clock generated from the add-in card input clock for PCI Express operation

on connector P13.

FPGA output used to select the fixed 125 MHz oscillator or the Clock

Synthesizer 2 output to be routed to GTP_DUAL tile X0Y5 MGTREFCLK

and SMA_MGT_GCLK global clock inputs. The ML555 board has a 4.7K Ω

pull-up resistor to 2.5V to provide default selection of clock synthesizer 2 as

the output of the Clock Mux block shown in Figure 3-8 and Figure 3-9 .

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

57

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